Multiport slave peripheral circuit designs are commonly a single monolithic block within an application specific integrated circuit (ASIC). The monolithic block approach creates difficulties in reusing all or portions of the design since the design is customized for the original ASIC application. Where portions of the design are reused, maintenance becomes difficult where the reused blocks are modified in order to be fully integrated with other blocks in the new application.
Another limitation of the monolithic block approach is encountered where bus traffic at a particular port varies among and/or within applications. For example, a multiport Advanced High-performance Bus (AHB) application may use a bus A to support very bursty but short traffic requests while a bus B may use 64-bit, long linear requests. A monolithic block optimized for bus A will not perform as well with bus B. What is desired is a reusable multiport slave peripheral architecture where a line buffer function can be repeated and scaled to meet a wide number of bus interfaces to any one or more different bus designs, speeds and widths.